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DL1 and DL2 - documentation not clear on a few things - Printable Version

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DL1 and DL2 - documentation not clear on a few things - silverdr - 2021-06-05

ytm Wrote:I have a few questions - the documentation is not clear/explicit on those:

1. If I start the second displaylist (VREG_DL2STROBE) what happens at the end of the frame? Do we get back to the beginning of DL1 or the beginning of DL2? If DL2 - how do I get back to DL1?

I admit this might not be completely clear so I'll update the docs shortly.

OTOH it is quite easy to verify with a few lines of VBASIC:

Code:
10 RACER0:RACER2
100 VCFG 0,0,1
110 VWAIT 130,0
120 VMOV $20,0:VMOV$21,0
130 VDELAYV 10
140 VMOV$20,14:VMOV$21,6
150 VMOV$41,0:VMOV$42,1:REM DL2 $0100
160 VMOV$43,0:REM DL2STROBE
170 REM VEND NOT NEEDED HERE
200 VCFG 0,$100,1
210 VWAIT 150,0
220 VMOV $20,0:VMOV$21,0
230 VDELAYV 10
240 VMOV$20,14:VMOV$21,6
999 VEND
1000 DLON
1999 END
READY.
If we'd be returning to DL2, then we would have only one black bar stable on the screen. Since there are two - this means we get back to DL1 ;-) Every raster (frame) we first execute the part located at $0000 and then the part located at $0100. This allows adding extra blocks of VASYL code and "jumping" around them without a need to cache/save/restore the initial address. If we look at it this way, then the DL2 is a kind of JMP equivalent (in addition to existing BRA) rather than a separate DL entity. There is a small caveat, which we have to be aware of, if we jump across memory banks. I'll cover it answering the next question.

RE: Documentation not clear on a few things - silverdr - 2021-06-05

ytm Wrote:2. Where do I set memory bank for DL1, and where for DL2? Or is it common for both? The description of DL2STROBE says: "Writing to this register will start execution of Display List pointed to by DLIST2(LH) from the next cycle. If MSB is set, also the RAM bank used by the Display List will change based on bits 0-2". It is unclear whether this affects only DL2 or both. There's no such description next to DLSTROBE

There is one place where the programmer can set which memory bank the displaylist will be executed from => DL2STROBE. Three LSBs (0-2) set the bank number, bit 3 is a bank change trigger. IOW - when upon writing to DL2STROBE the value written has its bit 3 set, displaylist processing switches to the bank selected with the three LSBs of that value. Please note that there was an error in "VASYL registers" documenation - the trigger bit is NOT the MSB. It is bit #3 (well.. MSB of the lower nybble :-)). Already corrected. DLSTROBE register does not have this kind of description  - there is no such functionality there.

Now, there is a caveat. Imagine that we start displaylist in BANK 0 and at some point we jump to and continue in – say – BANK 1. Once we complete the frame, VASYL jumps to the address pointed by DLISTL/DLISTH in currently selected bank! This means that because we switched to another bank - there is a good chance that VASYL will run off the rails. Therefore – unless we keep the bank we switched to on purpose – we have to restore the "original" bank before the end of current frame. An adapted version of the BASIC program from previous post shows this:

Code:
10 RACER0:RACER2:BANK 0
100 VCFG 0,0,1
110 VWAIT 130,0
120 VMOV $20,0:VMOV$21,0
130 VDELAYV 10
140 VMOV$20,14:VMOV$21,6
150 VMOV$41,0:VMOV$42,1:REM DL2 $0100
160 VMOV$43,8 OR 1:REM DL2STROBE BANK1
170 VEND:REM NOW NEEDED HERE (OR ANYWHERE IN BANK 0)
180 BANK 1
200 VCFG 0,$100,1
210 VWAIT 150,0
220 VMOV $20,0:VMOV$21,0
230 VDELAYV 10
240 VMOV$20,14:VMOV$21,6
980 VMOV$41,$12:VMOV$42,0:REM ADDR OF VEND IN BANK 0
990 VMOV$43,8 OR 0:REM DL2STROBE BANK0
999 REM VEND:REM NOT NEEED HERE NOW
1000 DLON
1999 END
READY.