Understanding the examples: demo_seq

[laubzega]

2. S_PADDING

From the docs, S_PADDING contains a 16bits value added to the bitmap sequencer's internal memory pointer at the end of every line.

What does it mean? At each rasterline, the sequencer skip n bytes. Is 1 byte representing a 8 pixels block ? Starting from the border ?
In the code it says:

Yes, one byte is 8 hires pixels or 4 multicolor ones, depending on the currently active graphics mode.

; - when end-of-line reached, continue to the next byte (no padding),
MOV    VREG_PBS_PADDINGL, 0
MOV    VREG_PBS_PADDINGH, 0

Continue to the next byte, which byte ? In the logo data ? is it to create a window in the logo's data?

Sort of. Look at this image. If the logo data is placed sequentially in memory (as is in our case), there is nothing to skip over at the end of line - hence we set both lo and hi byte to zero. But you could as well place each line of the logo in its own memory page (to scroll it around, or to be able to compute lines' starting addresses easily), and then you would like to instruct the sequencer to skip over empty regions at the end of a line, doing

MOV    VREG_PBS_PADDINGL, <(256 - logo_width_in_bytes)
MOV    VREG_PBS_PADDINGH, >(256 - logo_width_in_bytes)

Or you could e.g. skip negative number of bytes, to the beginning of the line that just finished displaying (-29 in this case), and the line would be displayed again.

3. S_STEP

From the docs, S_STEP contains a 16bits value added to the bitmap sequencer's internal memory pointer after every fetch.

In the code, I understand it increments the pointer of 1 byte, so I guess it means logo's data will be written sequentially except if the step is different than 1 ? Right ?

; - fetch bytes from successive memory addresses,
MOV    VREG_PBS_STEPL, 1
MOV    VREG_PBS_STEPH, 0

So, same guess? Is it to write the logo's data in a non contiguous manner (as I guess the step is not used while reading the logo's data, only for writing)

To clarify - in each cycle when the sequencer is active, the logo data is being read (or fetched) from the memory, to be immediately handed over to VIC. You could say that it is also being written (to VIC's bus), but I just want to make sure we are talking about the same thing.

As for S_STEP, yes, if data is sequential in memory (the typical case), the step is going to be 1 (again, see the picture). However, being able to change the fetching order can be helpful in creating visual effects, mirror and upside-down being the two demonstrated by the example code.

4. PBS_CONTROL

I guess this register trigger the sequencer but I did not find in the docs how it works. Where can I find the role of each bit?

Have you looked at the register description document? We realize it is not super detailed, but the sequencer document is coming along nicely, we're still planning it for this weekend (California time).


Also, all examples have been updated to keep VASYL data in its own segment, which simplified address references in display lists, and in general looks nicer. Thanks for helping improve the BeamRacer!